1. Field of the Invention
The present invention relates to a metallization method and apparatus for manufacturing semiconductor devices. More particularly, the present invention relates to a process for depositing a planarized metal film on a dielectric surface having nonuniform conductor material deposits formed thereon by using a warm physical vapor deposited metal. Even more particularly, the present invention relates to the selective metallization of apertures in insulative layers to form void-free interconnects between conducting layers, including apertures such as contacts or vias in high aspect ratio, i.e., sub-half micron wide aperture applications, and subsequent deposition of planar blanket films over surfaces suffering from loss of selectivity.
2. Background of the Related Art
Sub-half micron multilevel metallization is one of the key technologies for the next generation of very large scale integration ("VLSI"). The multilevel interconnect that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines or other features. High aspect ratios are features having a depth/width ratio of one or greater, typically of a depth of 1.2.mu.. Reliable formation of these interconnect features is very important to the success of VLSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Two conventional methods for depositing conducting film layers on substrates are chemical vapor deposition (CVD) and physical vapor deposition (PVD). Typically CVD provides better step coverage in very small aperture geometries, i.e., the deposition thickness at the base of the aperture is close to that on the adjacent field, while PVD provides desirable crystal structure and desirable orientation of the deposited film. Until recently, CVD and PVD processes were performed on different system platforms which required that the substrates first undergo one processing method and subsequently moved with an air break into a second platform for processing with another method. Transfer of the substrates from one platform to another decreases throughput of a substrate to complete device fabrication thereon, and exposes the most uppermost deposited surfaces to the atmosphere, typically forming an oxide layer. Therefore, it has not been considered effective to use the two processes to take advantage of the strengths of each process, i.e., good step coverage and good crystal orientation and reflectivity.
Two conventional methods for depositing conducting material by chemical vapor deposition ("CVD") include a blanket process and a selective process. CVD processes typically involve the deposition of a film layer which occurs when a component of the chemical vapor contacts a "nucleation site" on the substrate. The component attaches to the nucleation site, creating a deposit surface on which further deposition proceeds, i.e. grows laterally and vertically. A blanket CVD process typically deposits a film on the entire exposed surface of the substrate, including the sidewall and bottom of apertures, as well as the field, i.e., the uppermost exposed surface of the substrate, because surface exposed to the vapor serve as nucleation sites for deposition.
Selective CVD deposition is based on the fact that the decomposition of the CVD precursor gas to provide a deposition film usually requires a source of electrons from a conductive nucleation film. In accordance with a conventional selective CVD deposition process, the conducting film should grow in the bottom of an aperture where either a metal film, or doped silicon from the underlying conductive layer are exposed, but should not grow on the dielectric surface of the field and aperture walls. The underlying metal films and doped silicon are both conductive and supply the electrons needed for decomposition of the precursor gas and resulting deposition of the conducting film. The insulative film in its best form does not have free electron sites. Once deposition is initiated, the deposited metal is an electron donor. The result obtained through selective deposition is a "bottom-up" growth of a CVD conducting film in the holes, thereby enabling filling very small dimension (&lt;0.25 .mu.m), high aspect ratio (&gt;5:1) via or contact openings. Although in theory a selective CVD process should be capable of providing a defect free fill of an aperture on every occasion, in reality this is not the case.
Referring to FIG. 1, a drawing prepared from data obtained with a scanning electron microscope shows a top angle view of a patterned wafer which has been precleaned (sputtered with Ar for 60 seconds) and subsequently deposited with a selective CVD Al process. In actual practice of selective deposition processes, there are almost always defects on the surface of the dielectric and on the sidewalls of the apertures which provide free electrons and thus also serve as nucleation sites for CVD Al growth, causing unwanted deposition of conducting material in the form of nodules on the dielectric surface or field. The SEM shows the upper surface of the selectively deposited metal interconnects as well as nodules formed on defects in the dielectric layer surrounding the interconnects.
Referring to FIGS. 2 and 3, a top angle view and cross-sectional view of a patterned wafer are shown wherein approximately 6000 Angstroms of PVD Al at 150.degree. C. have been deposited over the CVD layer. The rough surface of the metal film of FIG. 2 is caused by the nodules shown in FIG. 1 even after deposition of a thick PVD metal layer. Such a rough surface interferes with subsequent photolithographic processing of the wafer. Additionally, FIG. 3 shows several grain boundaries between crystals having various orientations dictated by various nodules. These grain boundaries may cause failure of the integrated circuit.
Various methods have been used to minimize or eliminate the loss of selectivity that leads to nodule formation, especially in selective tungsten (W) technology. These methods have included, for example, changing the type of dielectric material, preconditioning the substrate surface prior to selective deposition, and post deposition chemical mechanical polishing (CMP) of the surface to remove any nodules which form on the substrate surface during selective deposition. While some of these methods have been able to reduce the extent of nodule formation, selectivity loss almost always occurs in selective CVD deposition processes. Furthermore, these methods complicate the processing steps required to form the desired circuit structure and significantly increase the expense of the integrated circuit manufacturing process. Some processes, such as CMP, cannot reach the sidewalls of the apertures, and thus any nodules formed in that location will remain. In addition, adding steps to the overall process increases the likelihood that defects may result in the formed structures due to handling and/or contamination mishaps.
Therefore, there exists a need for a metallization process for void-free filling of apertures, particularly high aspect ratio, sub-quarter micron wide apertures for forming interconnects and planarization of a subsequent conducting layer. More particularly, it would be desirable to have a simple process that takes advantage of the selectivity and good coverage of CVD processes and good planarization, crystal structure and reflectivity of PVD processes, while overcoming the loss of selectivity on the field encountered in CVD processes and perceived geometric limitations on PVD.